In the field of telephone connections and in telecommunication equipment generally, as a rule there exists a need for distribution of two clocking signals, herein called clock and synchronizing pulse rates, the latter one called "synch rate" in short, to various sub-equipments and components therein. This distribution is particularly wide in physically large connected systems, such as in the type of switches having various multiplexing stages and similar units. The clock rate has generally a high frequency and among other things defines borders for bits in the data flowing through the equipment and the synch rate has a low frequency and defines frame borders and similar things in the data signal. The number of signals transferring clock and synch information in an equipment such as a telecommunication switch station can be rather large and in the following the general expression "the clock distribution network" is used therefor. Telecommunication equipment in a magazine or cabinet, etc., has a considerable multitude of transmission components for rate distribution in the shape of cables, pins in back planes and electrical terminals, lines in back planes, etc. The space required for all such signal connections is considerable and costs money. As a rule, the number of pins in a connector is a small resource limiting the size of for example a switch.
In equipments having large requirements of their reliability the clock distribution network must of course also fulfil large reliability requirements. The reliability of the clock distribution network can be enhanced, in the conventional way, by introducing redundancy. If the clock distribution and the clock source are designed to include redundancy, i.e. that they may be duplicated or, as is supposed in the following herein, in the preferred case triplicated, a redundant and triplicated clocking structure can be maintained from clocking source to clocking receiver, however, in the receiver end one of the clocks must of course be selected for operational use by the respective equipment.
In previous systems not having redundancy, where clock rate and synch rate are to be distributed to all magazines and cabinets, as a rule two coaxial cable have been used to each receiver or user of the rates, one coaxial cable for the high frequent clock rate and one cable for the low frequency reference rate, that we call also the frame rate or the synch rate herein.
For distribution of clocking rates, where the high frequency clock is distributed separated from the low frequency synch rate, the precision must be great so that for example the pulses in the synch rate will not end up or be interpreted at the wrong one of the edges of the clock rate pulses. This poses among other things great requirements on the similarity of the lengths of the two cables used for clock and synch rate, respectively, in relation to each other and also in relation to other pairs of cables having other destinations in the system.
Distribution of a clock signal which has a very high frequency and by means of which circuits in telecommunication systems presently generally operate, in addition poses large requirements on the shielding of cables and connectors, etc. together with good grounding connections and similar things, so that interference protection and functionality can be provided and also maintained during a long time.
In for example large switches having circuits on circuit boards in magazines and cabinets there is thus a need for distributing a clock having a relatively high frequency and a rate having a lower frequency as a reference for frame structures, etc. Clock rate and synch rate can be distributed in the shape of a single, composite signal ("Composite Clock Signal"), herein called CLSY (CLock and SYnch), as described in the International Patent Application PCT/SE94/00321, which is incorporated herein by reference.
This signal comprises a clock frequency or clock rate that has a frequency considerably lower than the real system frequency at which the circuits of the system operate, i.e. is advantageously an even fraction thereof such as 1/36 thereof, and it further comprises a synch frequency or synch rate that is modulated on top of this clock frequency and advantageously is an even fraction, such as 1/640, thereof.
A phase-locked loop circuit, PLL, is provided with logic circuits interpreting the synch information in the composite CLSY signal and it also generates a clock signal having a frequency that is considerably higher than the clock frequency of the CLSY signal, such as for example in a similar way as above, 36 times thereof. The PLL issues the synch pulse with a precision in relation to the system clock that would have been very difficult to produce using conventional clock distribution on two separate lines.
The advantages of distributing a frequency in the shape of CLSY, that has a considerably lower frequency compared to the system clock and in addition is provided with synch information and of arranging for a PLL to generate the system clock rate together with synch rate are:
1. The signal can be distributed more easily from an EMC point of view, i.e. in regard of sensitivity to interference from the outside and in regard of its own interfering influence. The distribution medium must not have the same precision as in the case where system clock and synch rate would have been distributed separately. This implies that for instance a single optocable can be used. PA1 2. Pins and space in connectors and back planes, etc. are saved by using the same physical signal paths for both clock rate and synch rate. PA1 3. A very good precision can be achieved by the arrangement that the PLL generates both the system clock and the synch on the same chip and from the same signal.
Redundant clock distribution systems are disclosed in the documents discussed briefly hereinafter and also in other documents.
In the Japanese Patent Application JP-A 60-225982 clock pulse synchronization is described in a triplicated system. A harmful influence of errors is prevented by correction by means of majority decisions.
In U.S. Pat. No. 4,185,245 an arrangement is described for fault-tolerant clock signal distribution. First and second redundant clock signal sources are arranged. Clock receivers include sequential logic circuits for examining the two clock signals in order to ignore the clock signal pulse train that comes after the other one as to the phases thereof.
U.S. Pat. No. 4,489,412 discloses a network comprising supply of clock and synchronizing signals by means of clock distribution modules that perform majority voting for output signals from three oscillators.
U.S. Pat. No. 4,692,932 is related to triplicated clock distribution, each clock signal including a synchronizing signal. In the receivers R logic circuits for majority voting are included comprising three AND-gates and one NOR-gate in each receiver. These majority circuits pass only the input clock signal that has a phase position located between those of the other two clock signals. No tests are made of the quality of the received clock signals in the receivers in order to make the selection.
In U.S. Pat. No. 4,698,826 triplicated clock distribution is described. Each clock outputs a signal including a clock signal and a synchronizing signal.
U.S. Pat. No. 5,065,454 discloses a clock signal distribution arrangement having redundant clock generation. The distribution paths are duplicated for redundancy reasons.
The European Patent Application EP-A2 0 365 819 treats the problem of synchronizing the individual clocks in a multiprocessor system. A number of clock sources have each one its PLL circuit, see column 10, lines 31-58. The clocks transmit reference signals to each other which are subjected to a selection operation in each clock.
The European Patent Application EP-A2 0 366 326 treats the problem of ensuring, in a computer system in which a number of clock signals are derived from a main oscillator signal, that the clock signals appear at the right times where they are needed. It requires the introduction of a small time delay between the clock signals in order to compensate for differently long transmission paths. The solution described aims at reducing the risk of errors in the time delays of the different clock signals. A PLL circuit is used for maintaining :a phase relationship between each clock signal and a reference clock signal.
In U.S. Pat. No. 4,239,982 a fault-tolerant clock system is disclosed that is intended to produce system clock signals by means of several clock sources. Each clock source receives as input signals the clock signals generated from all other clock sources and contains receiver circuits for deriving a system clock signal from these clock sources. Each clock source generates and distributes to the other clock sources a clock signal that is locked in phase to the system clock derived from its clock receiver. The system allows the use of high clock frequencies comprising a minimum phase jitter between derived system clock signals.
In the European Patent Application EP-A2 0 303 916 four rate signals that are synchronous as to frequency and phase are generated, for providing timing for e.g. a computer system. The generation of the rate signals is made by means of four PLLs, the output signals of which are fed to four selector circuits, in which a type of majority voting is performed. The signal selected by a selector circuit is fed back to a definite one of the rate generators for controlling it. Delay circuits are introduced for adapting the phase position of the selected signals. Such delays cannot easily be introduced in the case where the clock signal contains both a clock and a synchronizing rate, the latter one having a low frequency.
In U.S. Pat. No. 4,105,900 a triplicated control system is disclosed in which three: redundant sensor signals are used, one of these signals providing precise information and the remaining two ones less precise information. A selection of signal according to a pre-programmed priority order is based on the operative state of the three sensors.